In the recent years it is becoming more important for semiconductor integrated circuit (IC) devices to meet endless demands for device miniaturization with higher integration density, which in turn wiring layers to drastic advances in microfabrication technology of metal oxide semiconductor (MOS) transistors for use with such ICs. Typically, one prior known MOS transistor includes a gate electrode formed on the main surface of a semiconductor substrate with a gate insulator layer laid therebetween, and a pair of spaced-apart source and drain electrodes formed in the main surface of the semiconductor substrate in a manner such that these are self-aligned with the gate electrode. The gate electrode and source/drain electrodes are such that each is connected to its overlying chip wiring layer through a conductive through hole in an interlayer dielectric film sandwiched between the electrode and the wiring layer for electrical connection to active and/or passive IC components operatively associated therewith. Such "internal" chip wiring layer are typically achieved by first forming in an overlying interlayer insulator a contact hole coupled to an associative wiring layer or electrode in an underlying layer, then forming a conductive connector material buried in the contact hole, and further forming an upper wiring layer connected to the conductor. The lower wiring layer and electrode are photolithographically fabricated using photo-etching process into a predefined pattern. Preferably, the pattern of contact holes connected thereto is formed by photo-etching alignment process so that the pattern is accurately aligned in position with those wiring layers in a low-level layer. It is also preferable that these contact holes thus formed are position-aligned with and appropriately connected to their overlying wiring layers in the upper level layer, through a similar position alignment procedure.
Unfortunately, semiconductor technologies are faced with difficulties in achieving precise position alignment between different patterns at different levels over a chip substrate, which would result in occurrence of pattern misalignment. This wiring layers to the risk of short-circuiting between unintentional short of wiring layers and electrodes. To avoid this, an extra area must be consumed as an alignment margin on the substrate surface. One example is that while the use of photo-lithography's minimal fabricatable size permits microfabrication of a rectangular or square contact hole to the extent that it measures 0.1 .mu.m in side length, addition of such "extra" alignment margin thereto results in an increase in "net" side length of underlying electrodes and wiring layers up to 0.5 .mu.m or wider.
Hence, providing the alignment margin per pattern serves as a serious bar to successful achievement of microfabrication or "down-sizing" of ICs as required.
Another problem encountered with the prior art approach is that the underlying wiring layers and electrodes of an increased pattern width due to addition of the alignment margin come with a parasitic resistance and parasitic capacitance, which can deteriorate high-speed characteristics of IC components.
One proposed approach for avoiding the problems associated with the prior art is to employ a self-aligned contact (SAC) structure, wherein contact holes are formed in self-alignment with electrodes and wiring layers in a lower layer.
Some prior art MOS transistor structures are shown in FIGS. 1a to 1c, wherein each transistor has contact holes H as formed by the SAC technique and connected to source/drain electrodes 15.
A respective one of the prior art MOS transistor shown in FIGS. 1a-1c is within one of element regions on the main surface of a semiconductor substrate 10, which regions are electrically insulated from each other by an element isolation region 11 as formed on the substrate surface. The MOS transistor consists essentially of a gate oxide film 12, a gate electrode 13, gate-sidewall dielectric films 14 on the opposite sidewalls of gate electrode 13, and source/drain electrodes 15 as formed by ion implantation with the gate electrode 13 and gate-sidewall dielectric films 14 being as a mask. An interlayer insulator 16 is formed on the surface of the MOS transistor, which film may be a fluorine doped low-dielectric-constant silicon oxide film or the like. Contact holes H are defined in the interlayer insulator 16, wherein contact wiring layers (not shown in the Fig.) are formed in these contact holes H for electrical connection of the source/drain electrodes 15 and gate electrode 13 to their associated wiring layers on the interlayer insulator 16.
FIG. 1a depicts the cross-sectional structure of one exemplary prior art MOS transistor, wherein misalignment results in one of the contact holes H being laterally offset exposing the sidewall of one gate-sidewall dielectric film 14 as shown. By forming the gate-sidewall dielectric film 14 using a silicon nitride film or the like which has a specified etching selection ratio with respect to silicon oxide of the interlayer insulator 16, it is possible to leave the gate-sidewall dielectric film 14, which in turn makes it possible to eliminate unwanted conduction with the semiconductor substrate 10 in those regions other than the intended regions. However, sufficient prevention of such conduction requires formation of the sidewall dielectric film 14 to a thickness greater than a standard thickness, which would result in contradiction with the device miniaturization or microfabrication of MOS tansistors required.
See FIG. 1b. This illustrates in cross-section another prior art MOS transistor structure, wherein misalignment causes one contact hole H to be offset rightward extending so that it rides on a local oxidation of silicon (LOCOS) element isolation region 11. Such offset of contact hole H toward the element isolation region 11 makes it impossible to prevent the element isolation region made of a silicon oxide film or the like from being partly etched away at its periphery D. This would result in an increase in current leakage between the semiconductor substrate 10 and a contact wiring layer being formed within the offset contact hole H. To avoid this problem, a scheme has been proposed for additionally doping an impurity of the same conductivity type as that of source/drain electrodes 15 by ion implantation into a selected region beneath the etching-removed element isolation region's periphery D to thereby extend the source/drain electrodes 15. However, this approach suffers from a problem that a leak current can flow between the source/drain and the neighboring semiconductor device components if such extension of the source/drain electrodes 15 renders narrower the element isolation region 11 to the extent that the resulting width is approximately 0.5 .mu.m or less.
See FIG. 1c, which shows a still another prior art MOS transistor employing a shallow trench isolation (STI) structure for use as the element isolation film as in the previous LOCOS element isolation region shown in FIGS. 1a-1b, wherein misalignment results in one contact hole H being offset toward the side of such STI region 11a. The STI region 11a can be deeply etched away at its periphery to have a "groove" deeper than the source/drain electrodes 15. If this is the case, the dielectricity is lowered between the semiconductor substrate 10 and source/drain electrodes 15 causing a problem such as noise generation or the like.
A yet another prior art contact hole formation method is shown in FIGS. 2a-2b, which depict some major steps in the fabrication of a MOS transistor that employs a silicon nitride film beneath the interlayer insulator to act as an etching stopper. The cross-sectional structures shown assumes that the pattem of contact hole H is offset toward the STI region 11a.
This method is such hat prior to formation of the prescribed interlayer insulator 16, an etching stopper film 14b of silicon nitride is formed by chemical vapor deposition (CVD) techniques on the main surface of the semiconductor substrate 10, which has the insulated gate electrode 13 and gate sidewall dielectric films 14a plus source/drain electrodes 15 formed as shown in FIG. 2a.
Then, as shown in FIG. 2a, an interlayer insulator 16 made of silicon oxide is formed; thereafter, contact holes H are defined therein for electrical connection to the source/drain electrodes 15. During this process, the progress of etching treatment is temporarily terminated on the surface of silicon nitride film 14b by utilizing the etching selection ratio (30:1) of silicon oxide of the interlayer insulator 16 versus silicon nitride. Subsequently, by utilizing here the inverse etching or "backetching" selection ratio (1:10) between the silicon nitride and silicon oxide, let the etching progress step at the surface of the silicon oxide film 14a as shown in FIG. 2a. Then, as shown in FIG. 2b, remove by etching the silicon oxide film 14a causing the semiconductor substrate 10 to be exposed on its main surface. However, in this case also, the etching treatment of silicon oxide film 14a can partly remove the STI region 11a made of the same material at the periphery thereof. As a result of such unwanted etching removal, current leakage can occur between the semiconductor substrate 10 and source/drain electrodes 15. In addition, production costs increase due to the need for additional process steps including deposition and etching of the interlayer insulator 16 and silicon nitride film 14b as well as silicon oxide film 14a.
Although the foregoing explanations are drawn to the fabrication of contact wiring layers in MOS transistors, similar problems will possibly arise with regard to formation of "via" contact holes for use in connecting a wiring layer pattern at the n-th level layer to a wiring layer at the (n+1)-th layer over a chip substrate. This will be explained in more detail with reference to FIG. 3 under the assumption that a via contact is formed between certain wiring layer patterns at the second and third level layers.
Prior to formation of such via contact, prepare a semiconductor substrate 10 with semiconductor device components (not shown in the Fig.) formed thereon; then, form a lamination of films on the main surface of the substrate, including a first or "lower" interlayer insulator 16, a wiring layer 17 in a first-level layer (first wiring layer) on the film 16, a second or interlayer insulator 26 covering the wiring layer 17, second-layer wiring layers 27a, 27b on the interlayer dielectric film 26, and a third or "upper" interlayer insulator 36 overlying these wiring layers 27a, 27b. A contact hole V for "via" contact is a through-hole for use in connecting the second wiring layer 27a and a third wiring layer being formed on the upper dielectric film 36. In this respect, it is not preferable that the via hole is used for connection with those wiring layers other than the second wiring layer 27a.
One serious problem associated with the prior art is that upon occurrence of positional misalignment of the kind stated supra, even the first wiring layer 17 can be exposed through the contact hole V resulting in unwanted shortcircuiting with a contact wiring layer as formed inside the contact hole V. This takes place even where the contact hole V does not reach the first wiring layer 17 per se. More specifically, it is difficult in such case also to completely attain the intended isolation by use of presently available interlayer insulators that tend to decrease in thickness with an increase in integration density so that the risk of leak current generation remains higher. Another problem is that the interlayer insulator with a reduced thickness due to formation of the contact hole V has an increased parasitic capacitance, which in turn behaves badly to increase cross-talk between the wiring layer in contact hole V and the first wiring layer or wiring layers.